module debounce(clk,key_in,key_out); //消抖
input clk;
input [7:0]key_in;
output [7:0] key_out;
reg [7:0] dout1,dout2,dout3;
wire [7:0] key_out;
always @(posedge clk)
begin
	dout1<=key_in;
	dout2<=dout1;
	dout3<=dout2;
end
assign key_out=dout1|dout2|dout3;
endmodule
